The improvements in the capacity and speed of semiconductor memory devices such as dynamic RAM have been quite remarkable. Particularly, in DDR SDRAM (Double Data Rate Synchronous DRAM), while internal operations are pipelined and commands supplied externally in synchronization with a clock are sequentially executed, high-speed system operation is achieved by performing data transfer at a rate twice the clock frequency. In the aforementioned DDR SDRAM, a high-speed data transfer is achieved by using a DLL (Delay Locked Loop) circuit and having internal circuits operate in synchronization with an external clock.
Meanwhile, the reduction of power consumption for semiconductor memory devices is demanded not only in the fields of devices operating with batteries such as laptops, but also in the field of servers. However, the aforementioned improvements in capacity and speed may increase power consumption.
Therefore, there is demand for a technology that boosts the capacity and speed of a semiconductor memory device without increasing power consumption.
Patent Document 1 describes a synchronous memory device that smoothly changes from auto-refresh mode to self-refresh mode in response to a power-down command.    [Patent Document 1] Japanese Patent Kokai Publication No. JP-P2006-31929A